Datasheet

Section 15 Universal Serial Bus Interface (USB)
Page 512 of 846 REJ09B0140-0900 Rev. 9.00
Sep 16, 2010
H8S/2215 Group
15.3.9 USB Endpoint Stall Register 0 (UESTL0)
UESTL0 is used to forcibly stall the endpoints for EP0 to EP3. While the bit is set to 1, the
corresponding endpoint returns a stall handshake to the host. However, note that EP3 (Isochronous
transfer) does not return a stall handshake.
The stall bit for endpoint 0 (EP0STL) is cleared automatically on reception of 8-bit command data
for which decoding is performed by the function. When the SetupTS flag in UIFR0 is set, a write
of 1 to the EP0STL bit is ignored. For details, refer to section 15.5.11, Stall Operations.
Bit Bit Name Initial Value R/W Description
7 EP3oSTL 0 R/W EP3o stall
0: Cancels the EP3o stall state
1: Places the EP3o stall state
6 EP3iSTL 0 R/W EP3i stall
0: Cancels the EP3i stall state
1: Places the EP3i stall state
When the EP3i is placed in the stall state, a 0-length
packet is returned for the first IN token. For the
following IN token, nothing is returned.
5 EP2oSTL 0 R/W EP2o stall
0: Cancels the EP2o stall state
1: Places the EP2o stall state
4 EP2iSTL 0 R/W EP2i stall
0: Cancels the EP2i stall state
1: Places the EP2i stall state
3 EP1iSTL 0 R/W EP1i stall
0: Cancels the EP1i stall state
1: Places the EP1i stall state
2 ,1 — All 0 R Reserved
These bits are always read as 0 and cannot be
modified.
0 EP0STL 0 R/W EP0 stall
0: Cancels the EP0 stall state
1: Places the EP0 stall state