Datasheet

Section 15 Universal Serial Bus Interface (USB)
Page 510 of 846 REJ09B0140-0900 Rev. 9.00
Sep 16, 2010
H8S/2215 Group
15.3.7 USBFIFO Clear Register 0 (UFCLR0)
UFCLR0 is a one-shot register used to clear the FIFO for each end point from EP0 to EP3.
Writing 1 to a bit clears the data in the corresponding FIFO. For IN FIFO, writing 1 to a bit in
UFCLR0 clears the data for which the corresponding PKTE bit in UTRG0 is cleared to 0 after
data write, or data that is validated by setting the corresponding PKTE bit in UTRG0. For OUT
FIFO, writing 1 to a bit in UFCLR0 clears data that has not been fixed during reception or
received data for which the corresponding RDFN bit is not set to 1. Accordingly, care must be
taken not to clear data that is currently being received or transmitted. EP2i, EP2o, EP3i, and EP3o
FIFOs, having a dual FIFO configuration, are cleared by entire FIFOs. Note that this trigger does
not clear the corresponding interrupt flag. For information on accessing this register, see 2.9.4,
Accessing Registers Containing Write-Only Bits.
Bit Bit Name Initial Value R/W Description
7 EP3oCLR 0 W EP3o clear
0: Performs no operation
1: Clears EP3o OUT FIFO
6 EP3iCLR 0 W EP3i clear
0: Performs no operation
1: Clears EP3i IN FIFO
5 EP2oCLR 0 W EP2o clear*
0: Performs no operation
1: Clears EP2o OUT FIFO
4 EP2iCLR 0 W EP2i clear
0: Performs no operation
1: Clears EP2i IN FIFO
3 EP1iCLR 0 W EP1i clear
0: Performs no operation
1: Clears EP1i IN FIFO
2 EP0oCLR 0 W EP0o clear
0: Performs no operation
1: Clears EP0o OUT FIFO
1 EP0iCLR 0 W EP0i clear
0: Performs no operation
1: Clears EP0i IN FIFO
0 — 0 R Reserved
This bit is always read as 0 and cannot be modified.