Datasheet

Section 15 Universal Serial Bus Interface (USB)
REJ09B0140-0900 Rev. 9.00 Page 509 of 846
Sep 16, 2010
H8S/2215 Group
Bit Bit Name Initial Value R/W Description
0 EP0sRDFN 0 W EP0s Read Completion
0: Performs no operation. A NAK handshake is
returned in response to transmit/receive requests
from the host in the data stage until 1 is written to
this bit.
1: Writes 1 to this bit after reading data for EP0s OUT
FIFO. After receiving the setup command, this
trigger enables the next packet to be received by the
EP0i and EP0o in the data stage. EP0s can always
be overwritten and receive data regardless of this
trigger.
Note: As triggers to EP3i and EP3o for Isochronous transfer are automatically generated each
time the SOF packet is received from the host, the user need not generate triggers to EP3i
and EP3o. Accordingly, data write to UEDR3i and data read from UEDR3o must be
completed before the next packet has been received.
15.3.6 USB Trigger Register 1 (UTRG1)
UTRG1 generates one-shot triggers to the FIFO for each endpoint EP4 and EP5. For information
on accessing this register, see 2.9.4, Accessing Registers Containing Write-Only Bits.
Bit Bit Name Initial Value R/W Description
7 to
3
— All 0 R Reserved
These bits are always read as 0 and cannot be
modified.
2 EP5iPKTE 0 W EP5i Packet Enable
0: Performs no operation
1: Generates a trigger to enable data transfer to
the EP5i IN FIFO.
1 EP4oRDFN 0 W EP4o Read Completion
0: Performs no operation
1: Writes 1 to this bit after reading data for EP4o OUT
FIFO. EP4o FIFO has a dual FIFO configuration.
This trigger is generated to the currently effective
FIFO.
0 EP4iPKTE 0 W EP4i Packet Enable
0: Performs no operation
1: Generates a trigger to enable data transfer to the
EP4i IN FIFO. EP4i FIFO has a dual FIFO
configuration. This trigger is generated for the
currently effective FIFO.