Datasheet

Section 13 Serial Communication Interface
Page 452 of 846 REJ09B0140-0900 Rev. 9.00
Sep 16, 2010
H8S/2215 Group
13.7.7 Serial Data Transmission (Except for Block Transfer Mode)
As data transmission in Smart Card interface mode involves error signal sampling and
retransmission processing, the operations are different from those in normal serial communication
interface mode (except for block transfer mode). Figure 13.30 illustrates the retransfer operation
when the SCI is in transmit mode.
1. If an error signal is sent back from the receiving end after transmission of one frame is
complete, the ERS bit in SSR is set to 1. If the RIE bit in SCR is enabled at this time, an ERI
interrupt request is generated. The ERS bit in SSR should be cleared to 0 by the time the next
parity bit is sampled.
2. The TEND bit in SSR is not set for a frame in which an error signal indicating an abnormality
is received. Data is retransferred from TDR to TSR, and retransmitted automatically.
3. If an error signal is not sent back from the receiving end, the ERS bit in SSR is not set.
Transmission of one frame, including a retransfer, is judged to have been completed, and the
TEND bit in SSR is set to 1. If the TIE bit in SCR is enabled at this time, a TXI interrupt
request is generated. Writing transmit data to TDR transfers the next transmit data.
Figure 13.32 shows a flowchart for transmission. A sequence of transmit operations can be
performed automatically by specifying the DTC or the DMAC to be activated with a TXI interrupt
source. In a transmit operation, the TDRE flag is set to 1 at the same time as the TEND flag in
SSR is set, and a TXI interrupt will be generated if the TIE bit in SCR has been set to 1. If the TXI
request is designated beforehand as a DTC
*
or the DMAC activation source, the DTC
*
or the
DMAC will be activated by the TXI request, and transfer of the transmit data will be carried out.
The TDRE and TEND flags are automatically cleared to 0 when data is transferred by the DTC
*
or the DMAC. In the event of an error, the SCI retransmits the same data automatically. During
this period, the TEND flag remains cleared to 0 and the DTC
*
or the DMAC is not activated.
Therefore, the SCI and DTC
*
or the DMAC will automatically transmit the specified number of
bytes in the event of an error, including retransmission. However, the ERS flag is not cleared
automatically when an error occurs, and so the RIE bit should be set to 1 beforehand so that an
ERI request will be generated in the event of an error, and the ERS flag will be cleared.
When performing transfer using the DMAC or the DTC, it is essential to set and enable the
DMAC or the DTC
*
before carrying out SCI setting. For details of the DMAC or the DTC
*
setting procedures, refer to section 8, Data Transfer Controller (DTC) or section 7, DMA
controller (DMAC).
Note: * The Flags are automatically cleared by the DTC when the DTC's DISEL bit is cleared
to 0 and the transfer counter value is not 0.