Datasheet

Section 13 Serial Communication Interface
Page 436 of 846 REJ09B0140-0900 Rev. 9.00
Sep 16, 2010
H8S/2215 Group
No
<End>
[1]
Yes
Initialization
Start transmission
Read TDRE flag in SSR [2]
Write transmit data to TDR and
set MPBT bit in SSR
No
Yes
No
Yes
Read TEND flag in SSR
[3]
No
Yes
[4]
Clear DR to 0 and set DDR to 1
Clear TE bit in SCR to 0
TDRE = 1
All data transmitted?
TEND = 1
Break output?
Clear TDRE flag to 0
[1] SCI initialization:
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1, a frame of
1s is output, and transmission is
enabled.
[2] SCI status check and transmit data
write:
Read SSR and check that the TDRE
flag is set to 1, then write transmit
data to TDR. Set the MPBT bit in SSR
to 0 or 1. Finally, clear the TDRE flag
to 0.
[3] Serial transmission continuation
procedure:
To continue serial transmission, be
sure to read 1 from the TDRE flag to
confirm that writing is possible, then
write data to TDR, and then clear the
TDRE flag to 0. Checking and
clearing of the TDRE flag is automatic
when the DMAC or the DTC* is
activated by a transmit data empty
interrupt (TXI) request, and data is
written to TDR.
[4] Break output at the end of serial
transmission:
To output a break in serial
transmission, set the port DDR to 1,
clear DR to 0, then clear the TE bit in
SCR to 0.
Note: * Checking and clearing of the
TDRE flag are performed
automatically by the DTC when
the DTC’s DISEL bit is cleared
to 0 and the transfer counter
value is not 0. Consequently, it
is necessary to use the CPU to
clear the TDRE flag if DISEL is
set to 1 or if the transfer
counter value is 0.
Figure 13.15 Sample Multiprocessor Serial Transmission Flowchart