Datasheet

Section 13 Serial Communication Interface
Page 404 of 846 REJ09B0140-0900 Rev. 9.00
Sep 16, 2010
H8S/2215 Group
Bit Bit Name Initial Value R/W Description
2
1
0
ACS2
ACS1
ACS0
0
0
0
R/W
R/W
R/W
Asynchronous Clock Source Select 2 to 0
These bits select the clock source in asynchronous mode.
When an average transfer rate is selected, the base clock is
set automatically regardless of the ABCS value. Note that
average transfer rates are not supported for operating
frequencies other than 10.667 MHz and 16 MHz. The
setting in bits ACS2 to ACS0 is valid when external clock
input is used (CKE1 = 1 in SCR) in asynchronous mode
(C/A = 0 in SMR). Figures 13.3 and 13.4 show setting
examples.
000: External clock input
001: 115.152 kbps average transfer rate (for φ = 10.667
MHz only) is selected
*
(SCI_0 operates on base clock
with frequency of 16 times transfer rate)
010: 460.606 kbps average transfer rate (for φ = 10.667
MHz only) is selected
*
(SCI_0 operates on base clock
with frequency of 8 times transfer rate)
011: Reserved
100: TPU clock input (AND of TIOCA1 and TIOCA2)
The signal generated by TIOCA1 and TIOCA2, which
are the compare match outputs for TPU_1 and TPU_2
or PWM outputs, is used as a base clock. Note that
IRQ0 and IRQ1 cannot be used since TIOCA1 and
TIOCA2 are used as outputs. The high pulse width for
TIOCA1 should be its low pulse width or less.
101: 115.196 kbps average transfer rate (for φ = 16 MHz
only) is selected (SCI_0 operates on base clock with
frequency of 16 times transfer rate)
110: 460.784 kbps average transfer rate (for φ = 16 MHz
only) is selected (SCI_0 operates on base clock with
frequency of 16 times transfer rate)
111: 720 kbps average transfer rate (for φ = 16 MHz only) is
selected (SCI_0 operates on base clock with
frequency of 8 times transfer rate)
Note: * Cannot be used in this LSI because the operating frequency φ in this LSI is 13 MHz or
greater.