Datasheet

Section 13 Serial Communication Interface
REJ09B0140-0900 Rev. 9.00 Page 391 of 846
Sep 16, 2010
H8S/2215 Group
Bit Bit Name Initial Value R/W Description
5 PE 0 R/W Parity Enable
When this bit is set to 1, the parity bit is added to
transmit data before transmission, and the parity bit is
checked in reception. Set this bit to 1 in smart card
interface mode.
4 O/E 0 R/W Parity Mode (valid only when the PE bit is 1)
0: Selects even parity
1: Selects odd parity
For details on the usage of this bit in smart card interface
mode, see section 13.7.2, Data Format (Except for Block
Transfer Mode).
3
2
BCP1
BCP0
0
0
R/W
R/W
Basic Clock Pulse 1,0
These bits select the number of basic clock cycles in a 1-
bit data transfer time in smart card interface mode.
00: 32 clock cycles (S = 32)
01: 64 clock cycles (S = 64)
10: 372 clock cycles (S = 372)
11: 256 clock cycles (S = 256)
For details, see section 13.7.5, Receive Data Sampling
Timing and Reception Margin. S is described in section
13.3.12, Bit Rate Register (BRR).
1
0
CKS1
CKS0
0
0
R/W
R/W
Clock Select 1,0
These bits select the clock source for the baud rate
generator.
00: φ clock (n = 0)
01: φ/4 clock (n = 1)
10: φ/16 clock (n = 2)
11: φ/64 clock (n = 3)
For the relation between the bit rate register setting and
the baud rate, see section 13.3.12, Bit Rate Register
(BRR). n is the decimal display of the value of n in BRR
(see section 13.3.12, Bit Rate Register (BRR)).