Datasheet

Section 11 8-Bit Timers (TMR)
Page 354 of 846 REJ09B0140-0900 Rev. 9.00
Sep 16, 2010
H8S/2215 Group
Table 11.2 Clock Input to TCNT and Count Condition
TCR
Bit 2 Bit 1 Bit 0
Channel
CKS2 CKS1 CKS0
Description
TMR_0 0 0 0 Clock input disabled
1 Internal clock, counted at falling edge of φ/8
1 0 Internal clock, counted at falling edge of φ/64
1 Internal clock, counted at falling edge of φ/8192
1 0 0 Count at TCNT1 overflow signal
*
TMR_1 0 0 0 Clock input disabled
1 Internal clock, counted at falling edge of φ/8
1 0 Internal clock, counted at falling edge of φ/64
1 Internal clock, counted at falling edge of φ/8192
1 0 0 Count at TCNT0 compare match A
*
All 1 0 1 External clock, counted at rising edge
1 0 External clock, counted at falling edge
1 1 External clock, counted at both rising and falling
edges
Note: * If the count input of TMR_0 is the TCNT_1 overflow signal and that of TMR_1 is the
TCNT_0 compare match signal, no incrementing clock is generated. This setting is
prohibited.
11.3.5 Timer Control/Status Registers (TCSR)
The TCSR registers display status flags, and control compare match output.