Datasheet

Section 11 8-Bit Timers (TMR)
REJ09B0140-0900 Rev. 9.00 Page 353 of 846
Sep 16, 2010
H8S/2215 Group
11.3.4 Time Control Registers (TCR)
The TCR registers select the clock source and the time at which TCNT is cleared, and enable
interrupts.
Bit Bit Name Initial Value R/W Description
7 CMIEB 0 R/W Compare Match Interrupt Enable B
Selects whether CMFB interrupt requests (CMIB) are
enabled or disabled when the CMFB flag in TCSR is
set to 1.
0: CMFB interrupt requests (CMIB) are disabled
1: CMFB interrupt requests (CMIB) are enabled
6 CMIEA 0 R/W Compare Match Interrupt Enable A
Selects whether CMFA interrupt requests (CMIA) are
enabled or disabled when the CMFA flag in TCSR is
set to 1.
0: CMFA interrupt requests (CMIA) are disabled
1: CMFA interrupt requests (CMIA) are enabled
5 OVIE 0 R/W Timer Overflow Interrupt Enable
Selects whether OVF interrupt requests (OVI) are
enabled or disabled when the OVF flag in TCSR is set
to 1.
0: OVF interrupt requests (OVI) are disabled
1: OVF interrupt requests (OVI) are enabled
4
3
CCLR1
CCLR0
0
0
R/W
R/W
Counter Clear 1 and 0
These bits select the method by which TCNT is
cleared.
00: Clear is disabled
01: Clear by compare match A
10: Clear by compare match B
11: Clear by rising edge of external reset input
2
1
0
CKS2
CKS1
CKS0
0
0
0
R/W
R/W
R/W
Clock Select 2 to 0
These bits select the clock input to TCNT and count
condition. See table 11.2.