Datasheet

Table Of Contents
Page xl of liv REJ09B0140-0900 Rev. 9.00
Sep 16, 2010
Figure 15.9 Example Flowchart of Suspend and Resume Interrupt Processing ......................... 553
Figure 15.10 Example Flowchart of Suspend and Remote-Wakeup Operations........................ 554
Figure 15.11 Example Flowchart of Remote-Wakeup Interrupt Processing .............................. 555
Figure 15.12 Control Transfer Stage Configuration................................................................... 556
Figure 15.13 Setup Stage Operation........................................................................................... 557
Figure 15.14 Data Stage Operation (Control-In)........................................................................ 559
Figure 15.15 Data Stage Operation (Control-Out)...................................................................... 560
Figure 15.16 Status Stage Operation (Control-In)...................................................................... 561
Figure 15.17 Status Stage Operation (Control-Out) ................................................................... 562
Figure 15.18 EP1i Interrupt-In Transfer Operation .................................................................... 563
Figure 15.19 EP2i Bulk-In Transfer Operation .......................................................................... 565
Figure 15.20 EP2o Bulk-Out Transfer Operation....................................................................... 567
Figure 15.21 EP3i Isochronous-In Transfer Operation............................................................... 569
Figure 15.22 EP3o Isochronous-Out Transfer Operation........................................................... 571
Figure 15.23 Forcible Stall by Firmware.................................................................................... 574
Figure 15.24 Automatic Stall by USB Function Module............................................................ 576
Figure 15.25 EP2iPKTE Operation in UTRG0 .......................................................................... 578
Figure 15.26 EP2oRDFN Operation in UTRG0......................................................................... 579
Figure 15.27 EP2iPKTE Operation in UTRG0 (Auto-Request)................................................. 581
Figure 15.28 EP2oRDFN Operation in UTRG0 (Auto-Request)............................................... 581
Figure 15.29 Endpoint Configuration Example.......................................................................... 582
Figure 15.30 USB External Circuit in Bus-Powered Mode
(When On-Chip Transceiver Is Used)................................................................... 587
Figure 15.31 USB External Circuit in Self-Powered Mode
(When On-Chip Transceiver Is Used)................................................................... 588
Figure 15.32 USB External Circuit in Bus-Powered Mode
(When External Transceiver Is Used)................................................................... 589
Figure 15.33 USB External Circuit in Self-Powered Mode
(When External Transceiver Is Used)................................................................... 590
Figure 15.34 10-Byte Data Reception ........................................................................................ 593
Figure 15.35 EP3o Data Reception............................................................................................. 594
Figure 15.36 Transition to and from Software Standby Mode ................................................... 597
Figure 15.37 USB Software Standby Mode Transition Timing ................................................. 598
Figure 15.38 TR Interrupt Flag Set Timing................................................................................ 599
Section 16 A/D Converter
Figure 16.1 Block Diagram of A/D Converter ........................................................................... 602
Figure 16.2 Access to ADDR (When Reading H'AA40)............................................................ 607
Figure 16.3 A/D Conversion Timing (Single-Chip Mode, Channel 1 Selected)........................ 609
Figure 16.4 A/D Conversion Timing (Scan Mode, Channels AN0 to AN3 Selected)................ 610