Datasheet

Section 10 16-Bit Timer Pulse Unit (TPU)
REJ09B0140-0900 Rev. 9.00 Page 343 of 846
Sep 16, 2010
H8S/2215 Group
Contention between TCNT Write and Clear Operations: If the counter clear signal is
generated in the T
2
state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT
write is not performed. Figure 10.45 shows the timing in this case.
Counter clear
signal
Write signal
Address
φ
TCNT address
TCNT
TCNT write cycle
T
1
T
2
N H'0000
Figure 10.45 Contention between TCNT Write and Clear Operations
Contention between TCNT Write and Increment Operations: If incrementing occurs in the T
2
state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented.
Figure 10.46 shows the timing in this case.
TCNT input
clock
Write signal
Address
φ
TCNT address
TCNT
TCNT write cycle
T
1
T
2
N M
TCNT write data
Figure 10.46 Contention between TCNT Write and Increment Operations