Datasheet

REJ09B0140-0900 Rev. 9.00 Page xxxv of liv
Sep 16, 2010
Figure 7.5 Operation in Idle Mode ............................................................................................. 176
Figure 7.6 Example of Idle Mode Setting Procedure..................................................................177
Figure 7.7 Operation in Repeat Mode.........................................................................................179
Figure 7.8 Example of Repeat Mode Setting Procedure.............................................................180
Figure 7.9 Operation in Normal Mode ....................................................................................... 182
Figure 7.10 Example of Normal Mode Setting Procedure.......................................................... 183
Figure 7.11 Operation in Block Transfer Mode (BLKDIR = 0)................................................. 185
Figure 7.12 Operation in Block Transfer Mode (BLKDIR = 1)................................................. 186
Figure 7.13 Operation Flow in Block Transfer Mode.................................................................187
Figure 7.14 Example of Block Transfer Mode Setting Procedure.............................................. 188
Figure 7.15 Example of DMA Transfer Bus Timing.................................................................. 191
Figure 7.16 Example of Short Address Mode Transfer..............................................................192
Figure 7.17 Example of Full Address Mode (Cycle Steal) Transfer...........................................193
Figure 7.18 Example of Full Address Mode (Burst Mode) Transfer..........................................194
Figure 7.19 Example of Full Address Mode (Block Transfer Mode) Transfer........................... 195
Figure 7.20 Example of DREQ Level Activated Normal Mode Transfer .................................. 196
Figure 7.21 Example of Multi-Channel Transfer........................................................................197
Figure 7.22 Example of Procedure for Continuing Transfer on Channel Interrupted by NMI
Interrupt................................................................................................................... 199
Figure 7.23 Example of Procedure for Forcibly Terminating DMAC Operation....................... 199
Figure 7.24 Example of Procedure for Clearing Full Address Mode ......................................... 200
Figure 7.25 Block Diagram of Transfer End/Transfer Break Interrupt ...................................... 201
Figure 7.26 DMAC Register Update Timing..............................................................................202
Figure 7.27 Contention between DMAC Register Update and CPU Read................................. 203
Section 8 Data Transfer Controller (DTC)
Figure 8.1 Block Diagram of DTC............................................................................................. 206
Figure 8.2 Block Diagram of DTC Activation Source Control .................................................. 213
Figure 8.3 Correspondence between DTC Vector Address and Register Information...............214
Figure 8.4 Correspondence between DTC Vector Address and Register Information............... 214
Figure 8.5 Flowchart of DTC Operation.....................................................................................216
Figure 8.6 Memory Mapping in Normal Mode .......................................................................... 218
Figure 8.7 Memory Mapping in Repeat Mode ........................................................................... 219
Figure 8.8 Memory Mapping in Block Transfer Mode...............................................................220
Figure 8.9 Chain Transfer Memory Map.................................................................................... 221
Figure 8.10 DTC Operation Timing (Example in Normal Mode or Repeat Mode).................... 222
Figure 8.11 DTC Operation Timing
(Example of Block Transfer Mode, with Block Size of 2)..................................... 223
Figure 8.12 DTC Operation Timing (Example of Chain Transfer) ............................................ 223