Datasheet

Section 10 16-Bit Timer Pulse Unit (TPU)
REJ09B0140-0900 Rev. 9.00 Page 289 of 846
Sep 16, 2010
H8S/2215 Group
10.3.1 Timer Control Register (TCR)
The TCR registers control the TCNT operation for each channel. The TPU has a total of three
TCR registers, one for each channel (channels 0 to 2). TCR register settings should be made only
when TCNT operation is stopped.
Bit Bit Name Initial value R/W Description
7
6
5
CCLR2
CCLR1
CCLR0
0
0
0
R/W
R/W
R/W
Counter Clear 2 to 0
These bits select the TCNTcounter clearing source. See
tables 10.3 and 10.4 for details.
4
3
CKEG1
CKEG0
0
0
R/W
R/W
Clock Edge 1 and 0
These bits select the input clock edge. When the internal
clock is counted using both edges, the input clock
frequency is halved (e.g., φ/4 both edges = φ/2 rising
edge). If phase counting mode is used on channels 1, 2,
4, and 5, this setting is ignored and the phase counting
mode setting has priority. Internal clock edge selection is
valid when the input clock is φ/4 or slower. If φ/1 is
selected as the input clock, this setting is ignored and
count at falling edge of φ is selected.
00: Count at rising edge
01: Count at falling edge
1×: Count at both edges
Legend: ×: Don’t care
2
1
0
TPSC2
TPSC1
TPSC0
0
0
0
R/W
R/W
R/W
Time Prescaler 2 to 0
These bits select the TCNT counter clock. The clock
source can be selected independently for each channel.
See tables 10.5 to 10.10 for details.