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ManualsBrandsRENESAS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TQFP 120 (14x14) 16-Bit 24 MHz I/O number 68
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Table Of Contents
Page xxxiv of liv REJ09B0140-0900 Rev. 9.00
Sep 16, 2010
Figure 5.2 Block Diagram of IRQn Interrupts.............................................................................. 92
Figure 5.3 Set Timing for IRQnF ................................................................................................. 93
Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0..... 97
Figure 5.5 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2..... 99
Figure 5.6 Interrupt Exception Handling.................................................................................... 100
Figure 5.7 Interrupt Control for DTC and DMAC ..................................................................... 103
Figure 5.8 Contention between Interrupt Generation and Disabling .......................................... 105
Section 6 Bus Controller
Figure 6.1 Block Diagram of Bus Controller.............................................................................. 110
Figure 6.2 Overview of Area Divisions...................................................................................... 121
Figure 6.3 CSn Signal Output Timing (n = 0 to 7)..................................................................... 124
Figure 6.4 On-Chip Memory Access Cycle................................................................................ 125
Figure 6.5 Pin States during On-Chip Memory Access.............................................................. 125
Figure 6.6 On-Chip Peripheral Module Access Cycle................................................................ 126
Figure 6.7 Pin States during On-Chip Peripheral Module Access.............................................. 126
Figure 6.8 Access Sizes and Data Alignment Control (8-Bit Access Space) ............................. 127
Figure 6.9 Access Sizes and Data Alignment Control (16-Bit Access Space) ........................... 128
Figure 6.10 Bus Timing for 8-Bit 2-State Access Space ............................................................ 129
Figure 6.11 Bus Timing for 8-Bit 3-State Access Space (Except Area 6).................................. 130
Figure 6.12 Bus Timing for Area 6............................................................................................. 131
Figure 6.13 Bus Timing for 16-Bit 2-State Access Space (1) (Even Address Byte Access)...... 132
Figure 6.14 Bus Timing for 16-Bit 2-State Access Space (2) (Odd Address Byte Access) ....... 133
Figure 6.15 Bus Timing for 16-Bit 2-State Access Space (3) (Word Access)............................ 134
Figure 6.16 Bus Timing for 16-Bit 3-State Access Space (1) (Even Address Byte Access)...... 135
Figure 6.17 Bus Timing for 16-Bit 3-State Access Space (2) (Odd Address Byte Access) ....... 136
Figure 6.18 Bus Timing for 16-Bit 3-State Access Space (3) (Word Access)............................ 137
Figure 6.19 Example of Wait State Insertion Timing................................................................. 139
Figure 6.20 Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 1).................. 140
Figure 6.21 Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0).................. 141
Figure 6.22 Example of Idle Cycle Operation (1) ...................................................................... 142
Figure 6.23 Example of Idle Cycle Operation (2) ...................................................................... 143
Figure 6.24 Relationship between Chip Select (CS) and Read (RD) ......................................... 144
Figure 6.25 Bus-Released State Transition Timing.................................................................... 146
Section 7 DMA Controller (DMAC)
Figure 7.1 Block Diagram of DMAC......................................................................................... 150
Figure 7.2 Areas for Register Re-Setting by DTC (Example: Channel 0A)............................... 170
Figure 7.3 Operation in Sequential Mode................................................................................... 174
Figure 7.4 Example of Sequential Mode Setting Procedure....................................................... 175