Datasheet

Section 9 I/O Ports
Page 278 of 846 REJ09B0140-0900 Rev. 9.00
Sep 16, 2010
H8S/2215 Group
9.12 Port G
Port G is a 5-bit I/O port that also has functioning as external interrupt input (IRQ7) and bus
control output (CS0 to CS3). The port G has the following registers.
• Port G data direction register (PGDDR)
• Port G data register (PGDR)
• Port G register (PORTG)
9.12.1 Port G Data Direction Register (PGDDR)
The individual bits of PGDDR specify input or output for the pins of port G. If port G is, an
undefined value will be read. Since this is a write-only register, bit manipulation instructions
should not be used to write to it. For details, see section 2.9.4, Accessing Registers Containing
Write-Only Bits.
Bit Bit Name Initial Value R/W Description
7 to
5
— Undefined — Reserved
These bits are undefined and cannot be modified.
4 PG4DDR 0/1
*
W
3 PG3DDR 0 W
2 PG2DDR 0 W
1 PG1DDR 0 W
0 PG0DDR 0 W
Modes 4 to 6
Setting a PGDDR bit to 1 makes the PG4 to PG1 pins bus
control signal outputs, while clearing the bit to 0 makes
the pin input ports. Signal outputs, while clearing the bit to
0 makes the pin input ports. Setting a PGDDR bit to 1
makes the PG0 pin an output port, while clearing the bit to
0 makes the pin an input port.
Mode 7
Setting a PGDDR bit to 1 makes the corresponding port G
pin an output port, while clearing the bit to 0 makes the
pin an input port.
Note: * In modes 4 and 5, set to 1; in modes 6 and 7 cleared to 0.