Datasheet

Section 9 I/O Ports
Page 248 of 846 REJ09B0140-0900 Rev. 9.00
Sep 16, 2010
H8S/2215 Group
9.6 Port A
Port A is a 4-bit I/O port that also functions as address bus (A19 to A16) output, external USB
transceiver output, and SCI_2 I/O, and interrupt input. The port A has the following registers.
• Port A data direction register (PADDR)
• Port A data register (PADR)
• Port A register (PORTA)
• Port A pull-up MOS control register (PAPCR)
• Port A open-drain control register (PAODR)
9.6.1 Port A Data Direction Register (PADDR)
The individual bits of PADDR specify input or output for the pins of port A. Since this is a write-
only register, bit manipulation instructions should not be used to write to it. For details, see section
2.9.4, Accessing Registers Containing Write-Only Bits.
Bit Bit Name Initial Value R/W Description
7 to
4
— Undefined — Reserved
These bits are undefined and cannot be modified.
3 PA3DDR 0 W
2 PA2DDR 0 W
1 PA1DDR 0 W
0 PA0DDR 0 W
Modes 4 to 6
If address output is enabled by the setting of bits AE3 to
AE0 in PFCR, the corresponding port A pins are address
outputs. When address output is disabled, setting a
PADDR bit to 1 makes the corresponding port A pin an
output port, while clearing the bit to 0 makes the pin an
input port.
Mode 7
Setting a PADDR bit to 1 makes the corresponding port A
pin an output port, while clearing the bit to 0 makes the
pin an input port.