Datasheet

Section 8 Data Transfer Controller (DTC)
Page 210 of 846 REJ09B0140-0900 Rev. 9.00
Sep 16, 2010
H8S/2215 Group
8.2.5 DTC Transfer Count Register A (CRA)
CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC.
In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65,536). It is
decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000.
In repeat mode or block transfer mode, the CRA is divided into two parts: the upper 8 bits
(CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL
functions as an 8-bit transfer counter (1 to 256). In block transfer mode, CRAH stores the block
size while CRAL functions as an 8-bit block size counter (1 to 256). CRAL is decremented by 1
every time data is transferred, and the contents of CRAH are sent when the count reaches H'00.
This operation is repeated.
8.2.6 DTC Transfer Count Register B (CRB)
CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in
block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1
every time data is transferred, and transfer ends when the count reaches H'0000.
8.2.7 DTC Enable Registers (DTCERA to DTCERF)
DTCER which is comprised of seven registers, DTCERA to DTCERF, is a register that specifies
DTC activation interrupt sources. The correspondence between interrupt sources and DTCE bits is
shown in table 8.2. For DTCE bit setting, use bit manipulation instructions such as BSET and
BCLR for reading and writing. If all interrupts are masked, multiple activation sources can be set
at one time (only at the initial setting) by writing data after executing a dummy read on the
relevant register.
Bit Bit Name Initial Value R/W Description
7
6
5
4
3
2
1
0
DTCEn7
DTCEn6
DTCEn5
DTCEn4
DTCEn3
DTCEn2
DTCEn1
DTCEn0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DTC Activation Enable 7 to 0
0: Prohibits DTC startup by an interrupt.
1: Selects a corresponding interrupt source as the DTC
startup source.
[Clearing conditions]
• When the DISEL bit is 1 and the data transfer has
ended
• When the specified number of transfers have ended
[Holding condition]
• These bits are not cleared when the DISEL bit is 0 and
the specified number of transfers have not ended