Datasheet

Section 8 Data Transfer Controller (DTC)
REJ09B0140-0900 Rev. 9.00 Page 209 of 846
Sep 16, 2010
H8S/2215 Group
8.2.2 DTC Mode Register B (MRB)
MRB selects the DTC operating mode.
Bit Bit Name Initial Value R/W Description
7 CHNE Undefined — DTC Chain Transfer Enable
This bit specifies a chain transfer. For details, refer to
section 8.5.4, Chain Transfer.
In data transfer with CHNE set to 1, determination of the
end of the specified number of transfers, clearing of the
interrupt source flag, and clearing of DTCER, are not
performed.
0: DTC data transfer completed (waiting for start)
1: DTC chain transfer (reads new register information and
transfers data)
6 DISEL Undefined — DTC Interrupt Select
This bit specifies whether CPU interrupt is disabled or
enabled after a data transfer.
0: Interrupt request is issued to the CPU when the
specified data transfer is completed.
1: DTC issues interrupt request to the CPU in every
data transfer (DTC does not clear the interrupt
request flag that is a cause of the activation).
5 to
0
— Undefined — Reserved
These bits have no effect on DTC operation, and the write
value should always be 0.
8.2.3 DTC Source Address Register (SAR)
SAR is a 24-bit register that designates the source address of data to be transferred by the DTC.
For word-size transfer, specify an even source address.
8.2.4 DTC Destination Address Register (DAR)
DAR is a 24-bit register that designates the destination address of data to be transferred by the
DTC. For word-size transfer, specify an even destination address.