Datasheet

Section 7 DMA Controller (DMAC)
Page 192 of 846 REJ09B0140-0900 Rev. 9.00
Sep 16, 2010
H8S/2215 Group
7.4.9 DMAC Bus Cycles (Dual Address Mode)
Short Address Mode: Figure 7.16 shows a transfer example in which TEND
*
output is enabled
and byte-size short address mode transfer (sequential/idle/repeat mode) is performed from external
8-bit, 2-state access space to internal I/O space.
φ
DMA read
RD
HWR
TEND*
LWR
DMA write DMA read DMA write DMA read DMA write
DMA
dead
Address bus
Note: * TEND output cannot be used with this LSI.
Bus release Bus release Bus release Bus releaseLast transfer cycle
Figure 7.16 Example of Short Address Mode Transfer
A one-byte or one-word transfer is performed for one transfer request, and after the transfer the
bus is released. While the bus is released one or more bus cycles are inserted by the CPU or DTC.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
In repeat mode, when TEND
*
output is enabled, TEND
*
output goes low in the transfer cycle in
which the transfer counter reaches 0.
Note: * TEND output cannot be used with this LSI.