Datasheet

Section 7 DMA Controller (DMAC)
Page 186 of 846 REJ09B0140-0900 Rev. 9.00
Sep 16, 2010
H8S/2215 Group
Figure 7.12 illustrates operation in block transfer mode when MARA is designated as a block area.
Address T
B
Address B
B
Transfer
Address T
A
Note:
Address T
A
= L
A
Address T
B
= L
B
Address B
A
= L
A
+ SAIDE · (–1)
SAID
· (2
DTSZ
· (N–1))
Address B
B
= L
B
+ DAIDE · (–1)
DAID
· (2
DTSZ
· (M · N–1))
L
A
= Value set in MARA
L
B
= Value set in MARB
N = Value set in ETCRB
M = Value set in ETCRAH and ETCRAL
Address B
A
1st block
2nd block
Nth block
Block area
Consecutive transfer
of M bytes or words
is performed in
rewponse to one
request
Figure 7.12 Operation in Block Transfer Mode (BLKDIR = 1)
ETCRAL is decremented by 1 each time a byte or word transfer is performed. In response to a
single transfer request, burst transfer is performed until the value in ETCRAL reaches H'00.
ETCRAL is then loaded with the value in ETCRAH. At this time, the value in the MAR register
for which a block designation has been given by the BLKDIR bit in DMACRA is restored in
accordance with the DTSZ, SAID/DAID, and SAIDE/DAIDE bits in DMACR.