Datasheet

Section 7 DMA Controller (DMAC)
REJ09B0140-0900 Rev. 9.00 Page 171 of 846
Sep 16, 2010
H8S/2215 Group
Bit Bit Name Initial Value R/W Description
7 to
4
— All 0 — Reserved
These bits are always read as 0 and cannot be modified.
3 WE1B 0 R/W Write Enable 1B
Enables or disables writes to all bits in DMACR1B, bits 11, 7,
and 3 in DMABCR by the DTC.
0: Writes to all bits in DMACR1B, bits 11, 7, and 3 in
DMABCR are disabled
1: Writes to all bits in DMACR1B, bits 11, 7, and 3 in
DMABCR are enabled
2 WE1A 0 R/W Write Enable 1A
Enables or disables writes to all bits in DMACR1A, and bits
10, 6, and 2 in DMABCR by the DTC.
0: Writes to all bits in DMACR1A, and bits 10, 6, and 2 in
DMABCR are disabled
1: Writes to all bits in DMACR1A, and bits 10, 6, and 2 in
DMABCR are enabled
1 WE0B 0 R/W Write Enable 0B
Enables or disables writes to all bits in DMACR0B, bits 9, 5,
and 1 in DMABCR by the DTC.
0: Writes to all bits in DMACR0B, bits 9, 5, and 1 in
DMABCR, are disabled
1: Writes to all bits in DMACR0B, bits 9, 5, and 1 in
DMABCR are enabled
0 WE0A 0 R/W Write Enable 0A
Enables or disables writes to all bits in DMACR0A, and bits 8,
4, and 0 in DMABCR by the DTC.
0: Writes to all bits in DMACR0A, and bits 8, 4, and 0 in
DMABCR are disabled
1: Writes to all bits in DMACR0A, and bits 8, 4, and 0 in
DMABCR are enabled
Writes by the DTC to bits 15 to 12 (FAE and SAE) in DMABCR are invalid regardless of the
DMAWER settings. These bits should be changed, if necessary, by CPU processing.
In writes by the DTC to bits 7 to 4 (DTE) in DMABCR, 1 can be written without first reading 0.
To reactivate a channel set to full address mode, write 1 to both Write Enable A and Write Enable
B for the channel to be reactivated.