Datasheet

Section 6 Bus Controller
Page 144 of 846 REJ09B0140-0900 Rev. 9.00
Sep 16, 2010
H8S/2215 Group
Relationship between Chip Select (CS) Signal and Read (RD) Signal: Depending on the
system’s load conditions, the RD signal may lag behind the CS signal. An example is shown in
figure 6.24.
In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap
between the bus cycle A RD signal and the bus cycle B CS signal.
Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and CS
signals.
In the initial state after reset release, idle cycle insertion (b) is set.
T
1
T
2
T
3
T
1
T
2
T
1
T
2
T
3
T
I
T
1
T
2
Address bus
φφ
Bus cycle A Bus cycle B
(a) Idle cycle not inserted
(ICIS1 = 0)
Possibility of overlap between
CS (area B) and RD
Address bus
Bus cycle A Bus cycle B
(b) Idle cycle inserted
(Initial value ICIS1 = 1)
CS (area A)
CS (area B)
RD RD
CS (area A)
CS (area B)
Figure 6.24 Relationship between Chip Select (CS) and Read (RD)
Table 6.4 shows pin states in an idle cycle.
Table 6.4 Pin States in Idle Cycle
Pins Pin State
A23 to A0 Contents of next bus cycle
D15 to D0 High impedance
CSn High
AS High
RD High
HWR High
LWR High