Datasheet

Section 6 Bus Controller
REJ09B0140-0900 Rev. 9.00 Page 143 of 846
Sep 16, 2010
H8S/2215 Group
Write after Read: If an external write occurs after an external read while the ICIS0 bit in BCRH
is set to 1, an idle cycle is inserted at the start of the write cycle.
Figure 6.23 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an
idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and
the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented.
T
1
T
2
T
3
T
1
T
2
T
1
T
2
T
3
T
I
T
1
T
2
Address bus
φφ
Bus cycle A
Data bus
Bus cycle B
Long output floating time
Data collision
(a) Idle cycle not inserted
(ICIS0 = 0)
Address bus
RD
Bus cycle A
Data bus
Bus cycle B
(b) Idle cycle inserted
(Initial value ICIS0 = 1)
CS (area A)
CS (area B)
RD
HWR
HWR
CS (area A)
CS (area B)
Figure 6.23 Example of Idle Cycle Operation (2)