Datasheet

Section 6 Bus Controller
Page 126 of 846 REJ09B0140-0900 Rev. 9.00
Sep 16, 2010
H8S/2215 Group
6.5.2 On-Chip Peripheral Module Access Timing
The on-chip peripheral modules are accessed in two states except on-chip USB. The data bus is
either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed.
Figure 6.6 shows the access timing for the on-chip peripheral modules. Figure 6.7 shows the pin
states.
T
1
T
2
φ
Internal address bus
Bus cycle
Address
Read data
Write data
Internal read signal
Internal data bus
Internal write signal
Internal data bus
Read
access
Write
access
Figure 6.6 On-Chip Peripheral Module Access Cycle
T
1
T
2
Bus cycle
Unchanged
Address bus
AS
RD
HWR, LWR
Data bus
φ
High
High
High
High-impedance state
Figure 6.7 Pin States during On-Chip Peripheral Module Access