Datasheet

Section 6 Bus Controller
REJ09B0140-0900 Rev. 9.00 Page 125 of 846
Sep 16, 2010
H8S/2215 Group
6.5.1 On-Chip Memory (ROM, RAM) Access Timing
On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and
word transfer instruction. Figure 6.4 shows the on-chip memory access cycle. Figure 6.5 shows the
pin states.
T
1
φ
Internal address bus
Bus cycle
Address
Read data
Write data
Internal read signal
Internal data bus
Internal write signal
Internal data bus
Read
access
Write
access
Figure 6.4 On-Chip Memory Access Cycle
Bus cycle
T
1
UnchangedAddress bus
AS
RD
HWR, LWR
Data bus
φ
High
High
High
High-impedance state
Figure 6.5 Pin States during On-Chip Memory Access