Datasheet

Section 6 Bus Controller
Page 124 of 846 REJ09B0140-0900 Rev. 9.00
Sep 16, 2010
H8S/2215 Group
RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding space becomes
external space.
When area 7 external space is accessed, the CS7 signal can be output.
Only the basic bus interface can be used for the area 7.
6.4.4 Chip Select Signals
This LSI can output chip select signals (CS0 to CS7) to areas 0 to 7, the signal being driven low
when the corresponding external space area is accessed. Figure 6.3 shows an example of CSn (n =
0 to 7) output timing. Enabling or disabling of the CSn signal is performed by setting the data
direction register (DDR) for the port corresponding to the particular CSn pin.
In ROM-disabled extended mode, the CS0 pin is placed in the output state after a power-on reset.
Pins CS1 to CS7 are placed in the input state after a power-on reset, and so the corresponding
DDR should be set to 1 when outputting signals CS1 to CS7.
In ROM-enabled extended mode, pins CS0 to CS7 are all placed in the input state after a power-on
reset, and so the corresponding DDR should be set to 1 when outputting signals CS0 to CS7. For
details, see section 9, I/O Ports.
Bus cycle
T
1
T
2
T
3
Area n external addressAddress bus
φ
CSn
Figure 6.3 CSn Signal Output Timing (n = 0 to 7)
6.5 Basic Timing
The CPU is driven by a system clock (φ), denoted by the symbol φ. The period from one rising
edge of φ to the next is referred to as a “state”. The memory cycle or bus cycle consists of one,
two, or three states. Different methods are used to access on-chip memory, on-chip peripheral
modules, and the external address space.