Datasheet

Table Of Contents
Section 6 Bus Controller
REJ09B0140-0900 Rev. 9.00 Page 109 of 846
Sep 16, 2010
H8S/2215 Group
Section 6 Bus Controller
This LSI has a built-in bus controller (BSC) that manages the external address space divided into
eight areas. The bus controller also has a bus arbitration function, and controls the operation of the
internal bus masters: the CPU, DMA controller (DMAC), and data transfer controller (DTC).
6.1 Features
Manages external address space in area units
Manages the external space as eight areas of 2 Mbytes
Bus specifications can be set independently for each area
Burst ROM interface can be set
Basic bus interface*
Chip select (CS0 to CS7 ) can be output for areas 0 to 7
8-bit access or 16-bit access can be selected for each area
2-state access or 3-state access can be selected for each area
Program wait states can be inserted for each area
Burst ROM interface
Burst ROM interface can be selected for area 0
One or two states can be selected for the burst cycle
Idle cycle insertion
Idle cycle can be inserted between consecutive read accesses to different areas
Idle cycle can be inserted before a write access to an external area immediately after a read
access to an external area
Bus arbitration
The on-chip bus arbiter arbitrates bus mastership among CPU, DMAC, and DTC
Other features
External bus release function
Note: * Chip select CS6 in area 6 is for the on-chip USB. Therefore it cannot be used as an
external area. 8-bit bus mode, 3-state access, and no program wait state should be set
for area 6.
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