Datasheet

Section 5 Interrupt Controller
Page 104 of 846 REJ09B0140-0900 Rev. 9.00
Sep 16, 2010
H8S/2215 Group
Determination of Priority: The DTC activation source is selected in accordance with the default
priority order, and is not affected by mask or priority levels. See section 8.4, Location of Register
Information and DTC Vector Table. The activation source is directly input to each channel of
DMAC.
Operation Order: If the same interrupt is selected as a DTC activation source and a CPU
interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception
handling.
If the same interrupt is selected as the DMAC activation factor and as the DTC activation factor or
CPU interrupt factor, these operate independently. They operate in accordance with the respective
operating states and bus priorities.
Table 5.6 shows the interrupt factor clear control and selection of interrupt factors by specification
of the DTA bit of DMAC’s DMABCR, DTC’s DTCERA to DTCERF’s DTCE bit, and the DISEL
bit of DTC’s MRB.
Table 5.6 Interrupt Source Selection and Clearing Control
Settings
DMAC DTC Interrupt Sources Selection/Clearing Control
DTA DTCE DISEL DMAC DTC CPU
0 0 * Δ X Ο
1 0 Δ Ο X
1 Δ Δ Ο
1 * * Ο X X
Legend:
Ο: The relevant interrupt is used. Interrupt source clearing is performed.
(The CPU should clear the source flag in the interrupt handling routine.)
Δ: The relevant interrupt is used. The interrupt source is not cleared.
X: The relevant bit cannot be used.
*: Don’t care
Notes on Use: The SCI interrupt source is cleared when the DMAC or DTC reads or writes to the
prescribed register, and is not dependent upon the DTA bit, DTCE bit, or DISEL bit.