Datasheet

Section 5 Interrupt Controller
REJ09B0140-0900 Rev. 9.00 Page 103 of 846
Sep 16, 2010
H8S/2215 Group
DMAC
DTCER
DTVECR
CPU
DTC
IRQ
interrupt
On-chip
supporting
module
Interrupt source
clear signal
Interrupt
request
Disenable signal Clear signal
Selection
circuit
Select
signal
DTC activation
request vector
number
CPU interrupt
request vector
number
I, I2 to I0
Clear signal
SWDTE
clear signal
Interrupt controller
Determination of
priority
Control logic
Clear signal
Figure 5.7 Interrupt Control for DTC and DMAC
Selection of Interrupt Source: An activation factor is directly input to each channel of the
DMAC. The activation factors for each channel of the DMAC are selected by the DTF3 to DTF0
bits of DMACR. The DTA bit of DMABCR can be used to select whether the selected activation
factors are managed by the DMAC. By setting the DTA bit to 1, the interrupt factor which was the
activation factor for that DMAC cannot act as the DTC activation factor or the CPU interrupt
factor.
Interrupt factors other than the interrupts managed by the DMAC are selected as DTC activation
request or CPU interrupt request by the DTCERA to DTCERF of DTC and the DTCE bit of
DTCERI.
By specifying the DISEL bit of the DTC’s MRB, it is possible to clear the DTCE bit to 0 after
DTC data transfer, and request a CPU interrupt.
If DTC carries out the designate number of data transfers and the transfer counter reads 0, after
DTC data transfer, the DTCE bit is also cleared to 0, CPU interrupt requested.