Datasheet

REJ09B0140-0900 Rev. 9.00 Page xv of liv
Sep 16, 2010
5.3.2 IRQ Enable Register (IER) .................................................................................88
5.3.3 IRQ Sense Control Registers H and L (ISCRH, ISCRL).................................... 89
5.3.4 IRQ Status Register (ISR)................................................................................... 91
5.4 Interrupt Sources................................................................................................................. 92
5.4.1 External Interrupts ..............................................................................................92
5.4.2 Internal Interrupts................................................................................................93
5.5 Interrupt Exception Handling Vector Table........................................................................ 93
5.6 Interrupt Control Modes and Interrupt Operation............................................................... 96
5.6.1 Interrupt Control Mode 0....................................................................................96
5.6.2 Interrupt Control Mode 2....................................................................................98
5.6.3 Interrupt Exception Handling Sequence ........................................................... 100
5.6.4 Interrupt Response Times ................................................................................. 101
5.6.5 DTC Activation by Interrupt............................................................................. 102
5.7 Usage Notes...................................................................................................................... 105
5.7.1 Contention between Interrupt Generation and Disabling.................................. 105
5.7.2 Instructions that Disable Interrupts................................................................... 106
5.7.3 Times when Interrupts Are Disabled ................................................................ 106
5.7.4 Interrupts during Execution of EEPMOV Instruction....................................... 106
5.7.5 IRQ Interrupt.....................................................................................................106
5.7.6 NMI Interrupts Usage Notes............................................................................. 107
Section 6 Bus Controller .................................................................................................... 109
6.1 Features.............................................................................................................................109
6.2 Input/Output Pins.............................................................................................................. 111
6.3 Register Descriptions........................................................................................................ 111
6.3.1 Bus Width Control Register (ABWCR)............................................................ 112
6.3.2 Access State Control Register (ASTCR) .......................................................... 113
6.3.3 Wait Control Registers H and L (WCRH, WCRL)...........................................114
6.3.4 Bus Control Register H (BCRH) ...................................................................... 118
6.3.5 Bus Control Register L (BCRL) ....................................................................... 119
6.3.6 Pin Function Control Register (PFCR) ............................................................. 120
6.4 Bus Control....................................................................................................................... 121
6.4.1 Area Divisions ..................................................................................................121
6.4.2 Bus Specifications............................................................................................. 122
6.4.3 Bus Interface for Each Area.............................................................................. 123
6.4.4 Chip Select Signals ........................................................................................... 124
6.5 Basic Timing.....................................................................................................................124
6.5.1 On-Chip Memory (ROM, RAM) Access Timing .............................................125
6.5.2 On-Chip Peripheral Module Access Timing..................................................... 126
6.5.3 External Address Space Access Timing ........................................................... 127