Datasheet

Page xiv of liv REJ09B0140-0900 Rev. 9.00
Sep 16, 2010
2.8 Processing States ................................................................................................................ 56
2.9 Usage Notes........................................................................................................................ 58
2.9.1 Note on TAS Instruction Usage.......................................................................... 58
2.9.2 STM/LTM Instruction Usage ............................................................................. 58
2.9.3 Note on Bit Manipulation Instructions................................................................ 58
2.9.4 Accessing Registers Containing Write-Only Bits............................................... 60
Section 3 MCU Operating Modes ..................................................................................... 63
3.1 Operating Mode Selection .................................................................................................. 63
3.2 Register Descriptions.......................................................................................................... 64
3.2.1 Mode Control Register (MDCR) ........................................................................ 64
3.2.2 System Control Register (SYSCR)..................................................................... 64
3.3 Operating Mode Descriptions............................................................................................. 66
3.3.1 Mode 4................................................................................................................ 66
3.3.2 Mode 5................................................................................................................ 66
3.3.3 Mode 6................................................................................................................ 67
3.3.4 Mode 7................................................................................................................ 67
3.3.5 Pin Functions ...................................................................................................... 68
3.4 Memory Map in Each Operating Mode.............................................................................. 69
Section 4 Exception Handling ............................................................................................ 73
4.1 Exception Handling Types and Priority.............................................................................. 73
4.2 Exception Sources and Exception Vector Table................................................................. 73
4.3 Reset ................................................................................................................................... 75
4.3.1 Reset Types......................................................................................................... 75
4.3.2 Reset Exception Handling................................................................................... 76
4.3.3 Interrupts after Reset........................................................................................... 78
4.3.4 State of On-Chip Peripheral Modules after Reset Release ................................. 78
4.4 Traces.................................................................................................................................. 79
4.5 Interrupts............................................................................................................................. 79
4.6 Trap Instruction .................................................................................................................. 80
4.7 Stack Status after Exception Handling................................................................................ 81
4.8 Notes on Use of the Stack................................................................................................... 82
Section 5 Interrupt Controller
............................................................................................. 83
5.1 Features............................................................................................................................... 83
5.2 Input/Output Pins................................................................................................................ 85
5.3 Register Descriptions.......................................................................................................... 86
5.3.1 Interrupt Priority Registers A to G, I to K, M
(IPRA to IPRG, IPRI to IPRK, IPRM) ............................................................... 87