Datasheet

Section 21 Clock Pulse Generator
Page 670 of 846 REJ09B0140-0900 Rev. 9.00
Sep 16, 2010
H8S/2215 Group
21.1.2 Low-Power Control Register (LPWRCR)
LPWRCR selects whether the oscillator’s built-in feedback resistor and duty adjustment circuit are
used with external clock input.
Bit Bit Name Initial Value R/W Description
7 to
4
— All 0 R/W Reserved
These bits can be read from or written to, but the write
value should always be 0.
3 RFCUT 0 R/W Built-in Feedback Resistor Control
Selects whether the oscillator’s built-in feedback resistor
and duty adjustment circuit are used with external clock
input. This bit should not be accessed when a crystal
oscillator is used.
After this bit is set when using external clock input, a
transition should initially be made to software standby
mode. Switching between use and non-use of the
oscillator’s built-in feedback resistor and duty adjustment
circuit is performed when the transition is made to software
standby mode.
0: System clock oscillator’s built-in feedback resistor
and duty adjustment circuit are used
1: System clock oscillator’s built-in feedback resistor
and duty adjustment circuit are not used
2 — 0 R/W Reserved
This bit can be read from or written to, but the write value
should always be 0.
1
0
STC1
STC0
0
0
R/W
R/W
Frequency Multiplication Factor
Specify the frequency multiplication factor of the PLL circuit
incorporated into the evaluation chip. The specified
frequency multiplication factor is valid after a transition to
software standby mode, watch mode, or subactive mode.
With this LSI, STC1 and STC0 must both be set to 1. After
a reset, STC1 and STC0 are both cleared to 0, and so
must be set to 1.
00: × 1
01: × 2 (Setting prohibited)
10: × 4 (Setting prohibited)
11: PLL is bypassed