Datasheet

Section 15 Universal Serial Bus Interface (USB)
REJ09B0140-0900 Rev. 9.00 Page 577 of 846
Sep 16, 2010
H8S/2215 Group
15.6 DMA Transfer Specifications
Two methods of USB request and auto request are available for the DMA transfer of USB data.
15.6.1 DMA Transfer by USB Request
(1) Overview
Only normal mode in full address mode (cycle steal mode) supports the transfer by a USB request
of the on-chip DMAC. Endpoints that can be transferred by the on-chip DMAC are EP2 and EP4
in Bulk transfer (corresponding registers are UEDR2i, UEDR2o, UEDR4i, and UEDR4o). In
DMA transfer, the USB module must be accessed as an external device in area 6. The USB
module cannot be accessed as a device with external ACK (single-address transfer cannot be
performed). 0-byte data transfer to EP2o or EP4o is ignored even if the DMA transfer is enabled
by setting the EP2oT1 or EP4oT1 bit of UDMAR to 1.
(2) On-Chip DMAC Settings
The on-chip DMAC must be specified as follows: A USB request (DREQ signal), activated by
low-level input, byte size, full-address mode transfer, and the DTA bit of DMABCR = 1. After
completing the DMA transfers of specified time, the DMAC automatically stops. Note, however,
that the USB module keeps the DREQ signal low while data to be transferred by the on-chip
DMAC remains regardless of the DMAC status.
(3) EP2i and EP4i DMA Transfer
The EP2iT1 and EP4iT1 bits of UDMAR enable DMA transfer. The EP2iT0 and EP4iT0 bits of
the UDMAR specify the DREQ signal to be used by the DMA transfer. When the EP2iT1 or
EP4iT1 is set to 1, the DREQ signal is driven low if at least one of EP2i and EP4i data FIFOs are
empty; the DREQ signal is driven high if both EP2i and EP4i data FIFOs are full.
(a) EP2iPKTE and EP4iPKTE Bits of UTRG
When DMA transfer is performed on EP2i and EP4i transmit data, the USB module automatically
performs the same processing as writing 1 to EP2iPKTE and EP4iPKTE if one data FIFO (64
bytes) becomes full. Accordingly, to transfer data of integral multiples of 64 bytes, the user need
not write EP2iPKTE and EP4iPKTE to 1. To transfer data of less than 64 bytes, the user must
write EP2iPKTE and EP4iPKTE to 1 using the DMA transfer end interrupt of the on-chip DMAC.
If the user writes 1 to EP2iPKTE and EP4iPKTE in cases other than the case when data of less
than 64 bytes is transferred, excess transfer occurs and correct operation cannot be guaranteed.
Figure 15.25 shows an example for transmitting 150 bytes of data from EP2i to the host. In this
case, internal processing the same as writing 1 to EP2iPKTE is automatically performed twice.