Datasheet

Section 15 Universal Serial Bus Interface (USB)
Page 518 of 846 REJ09B0140-0900 Rev. 9.00
Sep 16, 2010
H8S/2215 Group
15.3.24 USB Endpoint Receive Data Size Register 3o (UESZ3o)
UESZ3o is the receive data size register for endpoint 3o (for Isochronous_out transfer). UESZ3o
indicates the number of bytes of data to be received from the host.
Note that UESZ3o is decremented by 1 every time when 1 byte is read from UEDR3o.
The FIFO for endpoint 3o (for Isochronous_out transfer) has a dual-FIFO configuration. The data
size indicated by this register refers to the currently selected FIFO.
Bit Bit Name Initial Value R/W Description
7 to 0 D7 to D0 — R These bits indicate the size of data to be received in
Isochronous_out transfer
15.3.25 USB Endpoint Receive Data Size Register 4o (UESZ4o)
UESZ4o is the receive data size register for endpoint 4o (for Bulk_out transfer). UESZ4o indicates
the number of bytes of data to be received from the host.
Note that UESZ4o is decremented by 1 every time when 1 byte is read from UEDR4o.
The FIFO for endpoint 4o (for Bulk_out transfer) has a dual-FIFO configuration. The data size
indicated by this register refers to the currently selected FIFO.
Bit Bit Name Initial Value R/W Description
7 — — R Reserved
6 to 0 D6 toD0 — R These bits indicate the size of data to be received in
Bulk_out transfer
15.3.26 USB Interrupt Flag Register 0 (UIFR0)
UIFR0 is an interrupt flag register indicating the setup command reception, EP0 and EP1
transmission/reception, and bus reset states. If the corresponding bit is set to 1, the corresponding
EXIRQ0 or EXIRQ1 interrupt is requested to the CPU. A bit in this register can be cleared by
writing 0 to it. Writing 1 to a bit is invalid and causes no operation.
Consequently, to clear only a specific flag it is necessary to write 0 to the bit corresponding to the
flag to be cleared and 1 to all the other bits. (To clear bit 5 only, write H'DF.) The bit-clear
instruction is a read/modify/write instruction. There is a danger that the wrong bits may be cleared
if a new flag is set between the read and write. Therefore, the bit-clear instruction should not be
used to clear bits in this interrupt flag register.