Datasheet

Section 13 Serial Communication Interface
REJ09B0140-0900 Rev. 9.00 Page 449 of 846
Sep 16, 2010
H8S/2215 Group
bits in SCMR to 0. According to Smart Card regulations, clear the O/E bit in SMR to 0 to select
even parity mode.
Ds
AZZAAA ZAAA(Z) (Z) State
D7 D6 D5 D4 D3 D2 D1 D0 Dp
Figure 13.28 Inverse Convention (SDIR = SINV = O/E = 1)
With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level to
state Z, and transfer is performed in MSB-first order. The start character data for the above is
H'3F. For the inverse convention type, set the SDIR and SINV bits in SCMR to 1. According to
Smart Card regulations, even parity mode is the logic 0 level of the parity bit, and corresponds to
state Z. In this LSI, the SINV bit inverts only data bits D0 to D7. Therefore, set the O/E bit in
SMR to 1 to invert the parity bit for both transmission and reception.
13.7.3 Clock
Only an internal clock which is generated by the on-chip baud rate generator is used as a
transmit/receive clock. When an output clock is selected by setting CKE0 to 1, a clock with a
frequency S
*
times the bit rate is output from the SCK pin.
Note: * S is the value shown in section 13.3.12, Bit Rate Register (BRR).
13.7.4 Block Transfer Mode
Operation in block transfer mode is the same as that in the normal Smart Card interface mode,
except for the following points.
• In reception, though the parity check is performed, no error signal is output even if an error is
detected. However, the PER bit in SSR is set to 1 and must be cleared before receiving the
parity bit of the next frame.
• In transmission, a guard time of at least 1 etu is left between the end of the parity bit and the
start of the next frame.
• In transmission, because retransmission is not performed, the TEND flag is set to 1, 11.5 etu
after transmission start.
• As with the normal Smart Card interface, the ERS flag indicates the error signal status, but
since error signal transfer is not performed, this flag is always cleared to 0.