Datasheet

Section 13 Serial Communication Interface
Page 432 of 846 REJ09B0140-0900 Rev. 9.00
Sep 16, 2010
H8S/2215 Group
Yes
<End>
[1]
No
Initialization
Start reception
[2]
No
Yes
Read RDRF flag in SSR
[4]
[5]
Clear RE bit in SCR to 0
Read ORER, PER, and
FER flags in SSR
Error processing
(Continued on next page)
[3]
Read receive data in RDR, and
clear RDRF flag in SSR to 0
No
Yes
PER ∨ FER ∨ ORER = 1
RDRF = 1
All data received?
[1] SCI initialization:
The RxD pin is automatically designated as
the receive data input pin.
[2] [3] Receive error processing and break
detection:
If a receive error occurs, read the ORER,
PER, and FER flags in SSR to identify the
error. After performing the appropriate error
processing, ensure that the ORER, PER, and
FER flags are all cleared to 0. Reception
cannot be resumed if any of these flags are
set to 1. In the case of a framing error, a
break can be detected by reading the value
of the input port corresponding to the RxD
pin.
[4] SCI status check and receive data read:
Read SSR and check that RDRF = 1, then
read the receive data in RDR and clear the
RDRF flag to 0. Transition of the RDRF flag
from 0 to 1 can also be identified by an RXI
interrupt.
[5] Serial reception continuation procedure:
To continue serial reception, before the end
bit for the current frame is received, reading
the RDRF flag and RDR, and clearing the
RDRF flag to 0 should be finished. The RDRF
flag is cleared automatically when DMAC or
the DTC* is activated by a reception
complete interrupt (RXI) and the RDR value
is read.
Note: * Clearing of the RDRF flag are performed automatically by the DTC when the DTC's DISEL bit is cleared to 0
and the transfer counter value is not 0. Consequently, it is necessary to use the CPU to clear the RDRF flag if
DISEL is set to 1 or if the transfer counter value is 0.
Figure 13.13 Sample Serial Reception Data Flowchart (1)