Datasheet

Section 13 Serial Communication Interface
Page 408 of 846 REJ09B0140-0900 Rev. 9.00
Sep 16, 2010
H8S/2215 Group
9.6 MHz
9 MHz
Example for TPU clock generation for 562.5 kbps average transfer rate when φ = 24 MHz (TCS2 to TCS0 = B'001)
(1) 9.6-MHz base clock provided by TPU_0 is multiplied by 15/16 by TPU_1 to generate 9-MHz base clock (2) By making 1 bit = 16 base clocks, the average transfer will be 9 MHz/16 = 562.5 kbps
TPU and SCI settings
TIOCA0 output = 4.8 MHz TIOCC0 output = 4.8 MHz SCK0 Base clock = 9.6 MHz × 15/16 = 9 MHz (Average)
1 bit = Base clock × 16*
Average transfer rate = 9 MHz/16 = 562.5 kbps
Note: * The length of one bit varies according to the base clock synchronization.
12 563
Base clock (TIOCA0 + TIOCC0) output = 9.6 MHz Clock enable TIOCA1 output
4781112910 1314 1 215 16 3 4 7 856 910 131411 12 15 16 3 412 56 91078 11
12 563 4 7 8 11 12910 1314 1 215 3 4 7 856 910 131411 12 15 3 412 56 91078 11
12 563 4 7 8 11 12910 1314 16115 2 3 6 74 5 8 9 12 1310 11 14 1 215 16 3 4 7 856 9
• TCR_0 = H'20 [TCNT_0 cleared by TGRA_0 compare match, TCNT_0 incremented at rising edge of φ/1] • TCR_1 = H'2D [TCNT_1 cleared by TGRA_1 compare match, TCNT_1 incremented at falling edge of TCLKB • TMDR_0 = TMDR_1 = H'C2 [PWM mode 1] • TIORH_0 = H'21 [0 as TIOCA0 initial output, 0 output on TGRA_0 compare match, 1 output on TGRB_0 compare match] • TIORL_0 = H'21 [0 as TIOCC0 initial output, 0 output on TGRC_0 compare match, 1 output on TGRD_0 compare match] • TIOR_1 = H'21 [0 as TIOCA1 initial output, 0 output on TGRA_1 compare match, 1 output on TGRB_1 compare match] • TCNT_0 = TCNT_1 = H'0000 • TGRA_0 = H'0004, TGRB_0 = H'0002, TGRC_0 = H'0001, TGRD_0 = H'0000 • TGRA_1 = H'000F, TGRB_1 = H'0000 • SCR_0 = H'03 (external clock) • SEMRA_0 = H'14 (TCS2 to TCS0 = B'001, ABCS = 0, ACS2 to ACS0 = B'100) • SEMRB_0 = H'00 (ACS3 = 0)
TPU
TIOCA2
Clock enable
Base clock
φ
TIOCA1
TIOCC0
TIOCA0
TCLKA TCLKB
SCI_0
SCK0
D >CK
Q
Figure 13.5 Example of Average Transfer Rate Setting when TPU Clock Is Input (2)