Datasheet

Section 12 Watchdog Timer (WDT)
REJ09B0140-0900 Rev. 9.00 Page 369 of 846
Sep 16, 2010
H8S/2215 Group
Section 12 Watchdog Timer (WDT)
The watchdog timer (WDT) is an 8-bit timer that can generate an internal reset signal for this LSI
if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow.
When this watchdog function is not needed, the WDT can be used as an interval timer. In interval
timer operation, an interval timer interrupt is generated each time the counter overflows.
The block diagram of the WDT is shown in figure 12.1.
12.1 Features
• Selectable from eight counter input clocks
• Switchable between watchdog timer mode and interval timer mode
In watchdog timer mode
• If the counter overflows, it is possible to select whether this LSI is internally reset or not.
In interval timer mode
• If the counter overflows, the WDT generates an interval timer interrupt (WOVI).
Overflow
Interrupt
control
WOVI
(interrupt request
signal)
Internal reset signal*
Reset
control
RSTCSR TCNT TCSR
φ/2
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
Clock
Clock
select
Internal clock
sources
Bus
interface
Module bus
TCSR:
TCNT:
RSTCSR:
Note: * The type of internal reset signal depends on a register setting.
Timer control/status register
Timer counter
Reset control/status register
WDT
Legend:
Internal bus
Figure 12.1 Block Diagram of WDT
WDT0104A_000020020100