Datasheet

Section 11 8-Bit Timers (TMR)
REJ09B0140-0900 Rev. 9.00 Page 357 of 846
Sep 16, 2010
H8S/2215 Group
11.5 Operation Timing
11.5.1 TCNT Incrementation Timing
Figure 11.3 shows the count timing for internal clock input. Figure 11.4 shows the count timing
for external clock signal. Note that the external clock pulse width must be at least 1.5 states for
incrementation at a single edge, and at least 2.5 states for incrementation at both edges. The
counter will not increment correctly if the pulse width is less than these values.
φ
Internal clock
Clock input
to TCNT
TCNT
N – 1 N N + 1
Figure 11.3 Count Timing for Internal Clock Input
φ
External clock
input
Clock input
to TCNT
TCNT
N – 1 N N + 1
Figure 11.4 Count Timing for External Clock Input