Datasheet

REJ09B0140-0900 Rev. 9.00 Page xxxiii of liv
Sep 16, 2010
Figures
Section 1 Overview
Figure 1.1 Internal Block Diagram................................................................................................. 3
Figure 1.2 Pin Arrangement (TFP-120, TFP-120V)....................................................................... 4
Figure 1.3 Pin Arrangement (BP-112, BP-112V)........................................................................... 5
Section 2 CPU
Figure 2.1 Exception Vector Table (Normal Mode)..................................................................... 27
Figure 2.2 Stack Structure in Normal Mode................................................................................. 27
Figure 2.3 Exception Vector Table (Advanced Mode)................................................................. 28
Figure 2.4 Stack Structure in Advanced Mode............................................................................. 29
Figure 2.5 Memory Map............................................................................................................... 30
Figure 2.6 CPU Registers ............................................................................................................. 31
Figure 2.7 Usage of General Registers .........................................................................................32
Figure 2.8 Stack............................................................................................................................33
Figure 2.9 General Register Data Formats (1).............................................................................. 36
Figure 2.9 General Register Data Formats (2).............................................................................. 37
Figure 2.10 Memory Data Formats...............................................................................................38
Figure 2.11 Instruction Formats (Examples) ................................................................................ 50
Figure 2.12 Branch Address Specification in Memory Indirect Mode......................................... 53
Figure 2.13 State Transitions........................................................................................................ 57
Figure 2.14 Flowchart of Method for Accessing Registers Containing Write-Only Bits............. 61
Section 3 MCU Operating Modes
Figure 3.1 Memory Map in Each Operating Mode for HD64F2215 and HD64F2215U..............69
Figure 3.2 Memory Map in Each Operating Mode for HD6432215B.......................................... 70
Figure 3.3 Memory Map in Each Operating Mode for HD6432215C.......................................... 71
Figure 3.4 Memory Map in Each Operating Mode for HD64F2215R, HD64F2215RU,
HD64F2215T, HD64F2215TU and HD64F2215CU ..................................................72
Section 4 Exception Handling
Figure 4.1 Reset Sequence (Mode 4)............................................................................................77
Figure 4.2 Reset Sequence (Modes 6, 7) ...................................................................................... 78
Figure 4.3 Stack Status after Exception Handling........................................................................ 81
Figure 4.4 Operation when SP Value Is Odd................................................................................ 82
Section 5 Interrupt Controller
Figure 5.1 Block Diagram of Interrupt Controller........................................................................ 84