Datasheet

Section 7 DMA Controller (DMAC)
REJ09B0140-0900 Rev. 9.00 Page 169 of 846
Sep 16, 2010
H8S/2215 Group
Bit Bit Name Initial Value R/W Description
Data Transfer Interrupt Enable B
Enables or disables an interrupt to the CPU or DTC when
transfer is interrupted. If the DTIEB bit is set to 1 when DTME
= 0, the DMAC regards this as indicating a break in the
transfer, and issues a transfer break interrupt request to the
CPU or DTC. A transfer break interrupt can be canceled
either by clearing the DTIEB bit to 0 in the interrupt handling
routine, or by performing processing to continue transfer by
setting the DTME bit to 1.
3 DTIE1B 0 R/W Data Transfer Interrupt Enable 1B
Enables or disables the channel 1 transfer break interrupt.
0: Transfer break interrupt disabled
1: Transfer break interrupt enabled
Data Transfer End Interrupt Enable A
Enables or disables an interrupt to the CPU or DTC when
transfer ends. If the DTIEA bit is set to 1 when DTE = 0, the
DMAC regards this as indicating the end of a transfer, and
issues a transfer end interrupt request to the CPU or DTC. A
transfer end interrupt can be canceled either by clearing the
DTIEA bit to 0 in the interrupt handling routine, or by
performing processing to continue transfer by setting the DTE
bit to 1.
2 DTIE1A 0 R/W Data Transfer End Interrupt Enable 1A
Enables or disables the channel 1 transfer end interrupt.
0: Transfer end interrupt disabled
1: Transfer end interrupt enabled
1 DTIE0B 0 R/W Data Transfer Interrupt Enable 0B
Enables or disables the channel 0 transfer break interrupt.
0: Transfer break interrupt disabled
1: Transfer break interrupt enabled
0 DTIE0A 0 R/W Data Transfer End Interrupt Enable 0A
Enables or disables the channel 0 transfer end interrupt.
0: Transfer end interrupt disabled
1: Transfer end interrupt enabled