Datasheet

Section 7 DMA Controller (DMAC)
REJ09B0140-0900 Rev. 9.00 Page 163 of 846
Sep 16, 2010
H8S/2215 Group
Bit Bit Name Initial Value R/W Description
11
10
9
8
DTA1B
DTA1A
DTA0B
DTA0A
0
0
0
0
R/W
R/W
R/W
R/W
Data Transfer Acknowledge
These bits enable or disable clearing, when DMA transfer is
performed, of the internal interrupt source selected by the
data transfer factor setting.
When DTE = 1 and DTA = 1, the internal interrupt source
selected by the data transfer factor setting is cleared
automatically by DMA transfer. When DTE = 1 and DTA = 1,
the internal interrupt source selected by the data transfer
factor setting does not issue an interrupt request to the CPU
or DTC.
When DTE = 1 and DTA = 0, the internal interrupt source
selected by the data transfer factor setting is not cleared
when a transfer is performed, and can issue an interrupt
request to the CPU or DTC in parallel. In this case, the
interrupt source should be cleared by the CPU or DTC
transfer.
When DTE = 0, the internal interrupt source selected by the
data transfer factor setting issues an interrupt request to the
CPU or DTC regardless of the DTA bit setting.
0: Clearing of selected internal interrupt source at time of
DMA transfer is disabled
1: Clearing of selected internal interrupt source at time of
DMA transfer is enabled