Datasheet

ManualsBrandsRENESAS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LFBGA 112 (10x10) 16-Bit 24 MHz I/O number 68

Table Of Contents

Cover
Notice
General Precautions in the Handling of MPU/MCU Products
Configuration of This Manual
Preface
Main Revisions for This Edition
Contents
Section 1 Overview
- 1.1 Overview
- 1.2 Internal Block Diagram
- 1.3 Pin Arrangement
- 1.4 Pin Functions in Each Operating Mode
- 1.5 Pin Functions
Section 2 CPU
- 2.1 Features
- 2.2 CPU Operating Modes
  - 2.2.1 Normal Mode
  - 2.2.2 Advanced Mode
- 2.3 Address Space
- 2.4 Register Configuration
- 2.5 Data Formats
  - 2.5.1 General Register Data Formats
  - 2.5.2 Memory Data Formats
- 2.6 Instruction Set
  - 2.6.1 Table of Instructions Classified by Function
  - 2.6.2 Basic Instruction Formats
- 2.7 Addressing Modes and Effective Address Calculation
- 2.8 Processing States
- 2.9 Usage Notes
Section 3 MCU Operating Modes
- 3.1 Operating Mode Selection
- 3.2 Register Descriptions
  - 3.2.1 Mode Control Register (MDCR)
  - 3.2.2 System Control Register (SYSCR)
- 3.3 Operating Mode Descriptions
- 3.4 Memory Map in Each Operating Mode
Section 4 Exception Handling
- 4.1 Exception Handling Types and Priority
- 4.2 Exception Sources and Exception Vector Table
- 4.3 Reset
- 4.4 Traces
- 4.5 Interrupts
- 4.6 Trap Instruction
- 4.7 Stack Status after Exception Handling
- 4.8 Notes on Use of the Stack
Section 5 Interrupt Controller
- 5.1 Features
- 5.2 Input/Output Pins
- 5.3 Register Descriptions
- 5.4 Interrupt Sources
  - 5.4.1 External Interrupts
  - 5.4.2 Internal Interrupts
- 5.5 Interrupt Exception Handling Vector Table
- 5.6 Interrupt Control Modes and Interrupt Operation
- 5.7 Usage Notes
Section 6 Bus Controller
- 6.1 Features
- 6.2 Input/Output Pins
- 6.3 Register Descriptions
- 6.4 Bus Control
- 6.5 Basic Timing
- 6.6 Basic Bus Interface
- 6.7 urst ROM Interface
  - 6.7.1 Basic Timing
  - 6.7.2 Wait Control
- 6.8 Idle Cycle
- 6.9 Bus Release
  - 6.9.1 Notes on Bus Release
- 6.10 Bus Arbitration
- 6.11 Resets and the Bus Controller
Section 7 DMA Controller (DMAC)
- 7.1 Features
- 7.2 Register Configuration
- 7.3 Register Descriptions
- 7.4 Operation
- 7.5 Interrupts
- 7.6 Usage Notes
Section 8 Data Transfer Controller (DTC)
- 8.1 Features
- 8.2 Register Descriptions
- 8.3 Activation Sources
- 8.4 Location of Register Information and DTC Vector Table
- 8.5 Operation
- 8.6 Procedures for Using DTC
  - 8.6.1 Activation by Interrupt
  - 8.6.2 Activation by Software
- 8.7 Examples of Use of the DTC
  - 8.7.1 Normal Mode
  - 8.7.2 Software Activation
- 8.8 Usage Notes
Section 9 I/O Ports
- 9.1 Port 1
- 9.2 Port 3
- 9.3 Port 4
  - 9.3.1 Port 4 Register (PORT4)
  - 9.3.2 Pin Function
- 9.4 Port 7
- 9.5 Port 9
  - 9.5.1 Port 9 Register (PORT9)
  - 9.5.2 Pin Function
- 9.6 Port A
- 9.7 Port B
- 9.8 Port C
- 9.9 Port D
- 9.10 Port E
- 9.11 Port F
- 9.12 Port G
- 9.13 Handling of Unused Pins
Section 10 16-Bit Timer Pulse Unit (TPU)
- 10.1 Features
- 10.2 Input/Output Pins
- 10.3 Register Descriptions
- 10.4 Interface to Bus Master
  - 10.4.1 16-Bit Registers
  - 10.4.2 8-Bit Registers
- 10.5 Operation
- 10.6 Interrupts
- 10.7 Operation Timing
  - 10.7.1 Input/Output Timing
  - 10.7.2 Interrupt Signal Timing
- 10.8 Usage Notes
Section 11 8-Bit Timers (TMR)
- 11.1 Features
- 11.2 Input/Output Pins
- 11.3 Register Descriptions
- 11.4 Operation
  - 11.4.1 Pulse Output
- 11.5 Operation Timing
- 11.6 Operation with Cascaded Connection
  - 11.6.1 16-Bit Counter Mode
  - 11.6.2 Compare Match Count Mode
- 11.7 Interrupts
  - 11.7.1 Interrupt Sources and DTC Activation
  - 11.7.2 A/D Converter Activation
- 11.8 Usage Notes
Section 12 Watchdog Timer (WDT)
- 12.1 Features
- 12.2 Register Descriptions
- 12.3 Operation
- 12.4 Interrupts
- 12.5 Usage Notes
Section 13 Serial Communication Interface
- 13.1 Features
  - 13.1.1 Block Diagram
- 13.2 Input/Output Pins
- 13.3 Register Descriptions
- 13.4 Operation in Asynchronous Mode
- 13.5 Multiprocessor Communication Function
  - 13.5.1 Multiprocessor Serial Data Transmission
  - 13.5.2 Multiprocessor Serial Data Reception
- 13.6 Operation in Clocked Synchronous Mode
- 13.7 Operation in Smart Card Interface
- 13.8 SCI Select Function
- 13.9 Interrupts
  - 13.9.1 Interrupts in Normal Serial Communication Interface Mode
  - 13.9.2 Interrupts in Smart Card Interface Mode
- 13.10 Usage Notes
Section 14 Boundary Scan Function
- 14.1 Features
- 14.2 Pin Configuration
- 14.3 Register Descriptions
- 14.4 Boundary Scan Function Operation
  - 14.4.1 TAP Controller
- 14.5 Usage Notes
Section 15 Universal Serial Bus Interface (USB)
- 15.1 Features
- 15.2 Input/Output Pins
- 15.3 Register Descriptions
- 15.4 Interrupt Sources
- 15.5 Communication Operation
- 15.6 DMA Transfer Specifications
  - 15.6.1 DMA Transfer by USB Request
  - 15.6.2 DMA Transfer by Auto-Request
- 15.7 Endpoint Configuration Example
- 15.8 USB External Circuit Example
- 15.9 Usage Notes
Section 16 A/D Converter
- 16.1 Features
- 16.2 Input/Output Pins
- 16.3 Register Descriptions
- 16.4 Interface to Bus Master
- 16.5 Operation
- 16.6 Interrupts
- 16.7 A/D Conversion Precision Definitions
- 16.8 Usage Notes
Section 17 D/A Converter
- 17.1 Features
- 17.2 Input/Output Pins
- 17.3 Register Description
  - 17.3.1 D/A Data Register (DADR)
  - 17.3.2 D/A Control Register (DACR)
- 17.4 Operation
- 17.5 Usage Note
  - 17.5.1 Module Stop Mode Setting
Section 18 RAM
Section 19 Flash Memory (F-ZTAT Version)
- 19.1 Features
- 19.2 Mode Transitions
- 19.3 Block Configuration
- 19.4 Input/Output Pins
- 19.5 Register Descriptions
- 19.6 On-Board Programming Modes
- 19.7 Flash Memory Emulation in RAM
- 19.8 Flash Memory Programming/Erasing
  - 19.8.1 Program/Program-Verify
  - 19.8.2 Erase/Erase-Verify
- 19.9 Program/Erase Protection
- 19.10 Interrupt Handling when Programming/Erasing Flash Memory
- 19.11 Programmer Mode
- 19.12 Power-Down States for Flash Memory
- 19.13 Flash Memory Programming and Erasing Precautions
- 19.14 Note on Switching from F-ZTAT Version to Masked ROM Version
Section 20 Masked ROM
- 20.1 Features
Section 21 Clock Pulse Generator
- 21.1 Register Descriptions
  - 21.1.1 System Clock Control Register (SCKCR)
  - 21.1.2 Low-Power Control Register (LPWRCR)
- 21.2 System Clock Oscillator
- 21.3 Duty Adjustment Circuit
- 21.4 Medium-Speed Clock Divider
- 21.5 Bus Master Clock Selection Circuit
- 21.6 USB Operating Clock (48 MHz)
- 21.7 PLL Circuit for USB
- 21.8 Usage Notes
Section 22 Power-Down Modes
- 22.1 Register Descriptions
  - 22.1.1 Standby Control Register (SBYCR)
  - 22.1.2 Module Stop Control Registers A to C (MSTPCRA to MSTPCRC)
- 22.2 Medium-Speed Mode
- 22.3 Sleep Mode
  - 22.3.1 Transition to Sleep Mode
  - 22.3.2 Exiting Sleep Mode
- 22.4 Software Standby Mode
- 22.5 Hardware Standby Mode
- 22.6 Module Stop Mode
- 22.7 φClock Output Disabling Function
- 22.8 Usage Notes
Section 23 List of Registers
- 23.1 Register Addresses (Address Order)
- 23.2 Register Bits
- 23.3 Register States in Each Operating Mode
Section 24 Electrical Characteristics (H8S/2215)
- 24.1 Absolute Maximum Ratings
- 24.2 Power Supply Voltage and Operating Frequency Range
- 24.3 DC Characteristics
- 24.4 AC Characteristics
- 24.5 USB Characteristics
- 24.6 A/D Conversion Characteristics
- 24.7 D/A Conversion Characteristics
- 24.8 Flash Memory Characteristics
- 24.9 Usage Note
Section 25 Electrical Characteristics (H8S/2215R)
- 25.1 Absolute Maximum Ratings
- 25.2 Power Supply Voltage and Operating Frequency Range
- 25.3 DC Characteristics
- 25.4 AC Characteristics
- 25.5 USB Characteristics
- 25.6 A/D Conversion Characteristics
- 25.7 D/A Conversion Characteristics
- 25.8 Flash Memory Characteristics
- 25.9 Usage Note
Section 26 Electrical Characteristics (H8S/2215T)
- 26.1 Absolute Maximum Ratings
- 26.2 Power Supply Voltage and Operating Frequency Range
- 26.3 DC Characteristics
- 26.4 AC Characteristics
- 26.5 USB Characteristics
- 26.6 A/D Conversion Characteristics
- 26.7 D/A Conversion Characteristics
- 26.8 Flash Memory Characteristics
- 26.9 Usage Note
Section 27 Electrical Characteristics (H8S/2215C)
- 27.1 Absolute Maximum Ratings
- 27.2 Power Supply Voltage and Operating Frequency Range
- 27.3 DC Characteristics
- 27.4 AC Characteristics
- 27.5 USB Characteristics
- 27.6 A/D Conversion Characteristics
- 27.7 D/A Conversion Characteristics
- 27.8 Flash Memory Characteristics
- 27.9 Usage Note
Appendix
- A. I/O Port States in Each Processing State
- B. Product Model Lineup
- C. Package Dimensions
Index
Colophon
Address List
Back Cover

Section 6 Bus Controller

REJ09B0140-0900 Rev. 9.00 Page 137 of 846

Sep 16, 2010

H8S/2215 Group

Bus cycle

T

1

T

2

Address bus

φ

CSn

AS

RD

D15 to D8

Valid

D7 to D0

Valid

Read

HWR

LWR

D15 to D8

Valid

D7 to D0

Valid

Write

Note: n = 0 to 7

T

3

Figure 6.18 Bus Timing for 16-Bit 3-State Access Space (3) (Word Access)