Datasheet

Section 5 Interrupt Controller
REJ09B0140-0900 Rev. 9.00 Page 91 of 846
Sep 16, 2010
H8S/2215 Group
Bit Bit Name Initial Value R/W Description
1
0
IRQ0SCB
IRQ0SCA
0
0
R/W
R/W
IRQ0 Sense Control B
IRQ0 Sense Control A
00: Interrupt request generated at IRQ0 input low level
01: Interrupt request generated at falling edge of IRQ0
input
10: Interrupt request generated at rising edge of IRQ0
input
11: Interrupt request generated at both falling and
rising edges of IRQ0 input
5.3.4 IRQ Status Register (ISR)
ISR indicates the status of IRQ7 to IRQ0 interrupt requests. Only 0 should be written to these bits
for clearing the flag.
Bit Bit Name Initial Value R/W Description
7 IRQ7F 0 R/(W)
*
6 IRQ6F 0 R/(W)
*
5 IRQ5F 0 R/(W)
*
4 IRQ4F 0 R/(W)
*
3 IRQ3F 0 R/(W)
*
2 IRQ2F 0 R/(W)
*
1 IRQ1F 0 R/(W)
*
0 IRQ0F 0 R/(W)
*
[Setting condition]
• When the interrupt source selected by the ISCR
registers occurs
[Clearing conditions]
• Cleared by reading IRQnF flag when IRQnF = 1,
then writing 0 to IRQnF flag
• When interrupt exception handling is executed
when low-level detection is set and, IRQn input is
high
• When IRQn interrupt exception handling is
executed when falling, rising, or both-edge
detection is set
• When the DTC is activated by an IRQn interrupt,
and the DISEL bit in MRB of the DTC is cleared
to 0
Note: * The write value should always be 0 to clear the flag.