Datasheet

Section 22 Electrical Characteristics
Rev.7.00 Dec. 24, 2008 Page 676 of 698
REJ09B0074-0700
Condition A Condition B Condition
C,D
Item Symbol Min. Max. Min. Max. Min. Max. Unit
Test
Conditions
SCI Input
clock
Asynchro-
nous
t
Scyc
4 — 4 — 4 — t
cyc
Figure
22.15
cycle
Synchro-
nous
6 — 6 — 6 —
Input clock pulse
width
t
SCKW
0.4 0.6 0.4 0.6 0.4 0.6 t
Scyc
Input clock rise time t
SCKr
— 1.5 — 1.5 — 1.5 t
cyc
Input clock fall time t
SCKf
— 1.5 — 1.5 — 1.5
Transmit data delay
time
t
TXD
— 150 — 60 — 40 ns Figure
22.16
Receive data setup
time (synchronous)
t
RXS
150 — 60 — 40 —
Receive data hold
time (synchronous)
t
RXH
150 — 60 — 40 —
A/D
converter
Trigger input setup
time
t
TRGS
60 — 40 — 30 — ns Figure
22.17
TCK cycle time t
Tcyc
166.6 — 62.5 — 41.6 — ns Boundary
scan
TCK high level pulse
width
t
TCKH
0.4 0.6 0.4 0.6 0.4 0.6 t
Tcyc
TCK low level pulse
width
t
TCKL
0.4 0.6 0.4 0.6 0.4 0.6 t
Tcyc
Figure
22.18
TRST pulse width t
TRSW
20 — 20 — 20 — t
Tcyc
TRST setup time t
TRSS
350 — 250 — 250 — ns
Figure
22.19
TDI setup time t
TDIS
80 — 30 — 20 — ns
TDI hold time t
TDIH
10 — 10 — 10 —
TMS setup time t
TMSS
80 — 30 — 20 —
Figure
22.20
TMS hold time t
TMSH
10 — 10 — 10 —
TDO delay time t
TDOD
— 100 — 40 — 35