Datasheet

Section 22 Electrical Characteristics
Rev.7.00 Dec. 24, 2008 Page 675 of 698
REJ09B0074-0700
22.4.4 Timing of On-Chip Supporting Modules
Table 22.7 lists the timing of on-chip supporting modules.
Table 22.7 Timing of On-Chip Supporting Modules
Condition A: V
CC
= PLL V
CC
= Dr V
CC
= 2.4 V to 3.6 V, Vref = 2.4 V to V
CC
, V
SS
= PLLV
SS
=
Dr V
SS
= 0 V, f = 32.768 kHz, 6 MHz, T
a
= –20°C to +75°C (regular specifications),
T
a
= –40°C to +85°C (wide-range specifications)
Condition B: V
CC
= PLL V
CC
= Dr V
CC
= 2.7 V to 3.6 V, Vref = 2.7 V to V
CC
, V
SS
= PLLV
SS
=
Dr V
SS
= 0 V, f = 32.768 kHz, 6 MHz to 16 MHz, T
a
= –20°C to +75°C (regular
specifications), T
a
= –40°C to +85°C (wide-range specifications)
Condition C: V
CC
= PLL V
CC
= Dr V
CC
= 3.0 V to 3.6 V, Vref = 3.0 V to V
CC
, V
SS
= PLLV
SS
=
Dr V
SS
= 0 V, f = 32.768 kHz, 6 MHz to 24 MHz, T
a
= –20°C to +75°C (regular
specifications), T
a
= –40°C to +85°C (wide-range specifications)
Condition D: V
CC
= PLL V
CC
= Dr V
CC
= 3.0 V to 3.6 V, Vref = 3.0 V to V
CC
, V
SS
= PLLV
SS
=
Dr V
SS
= 0 V, f = 32.768 kHz, 16 MHz to 24 MHz, T
a
= −20°C to +75°C (regular
specifications), T
a
= −40°C to +85°C (wide-range specifications)
Condition A Condition B Condition C, D
Item Symbol Min. Max. Min. Max. Min. Max. Unit
Test
Conditions
I/O port Output data delay
time
t
PWD
— 150 — 60 — 40 ns Figure
22.12
Input data setup time t
PRS
80 — 50 — 30 —
Input data hold time t
PRH
50 — 50 — 30 —
TPU Timer output delay
time
t
TOCD
— 150 — 60 — 40 ns Figure
22.13
Timer input setup
time
t
TICS
60 — 40 — 30 —
Timer clock input
setup time
t
TCKS
60 — 40 — 30 — ns Figure
22.14
Single
edge
t
TCKWH
1.5 — 1.5 — 1.5 — t
cyc
Timer
clock
pulse
width
Both
edges
t
TCKWL
2.5 — 2.5 — 2.5 —