Datasheet

Section 22 Electrical Characteristics
Rev.7.00 Dec. 24, 2008 Page 665 of 698
REJ09B0074-0700
Condition A Condition B Condition C Condition D
Item Symbol Min. Max. Min. Max. Min. Max. Min. Max. Unit
Test
Conditions
External clock output
stabilization delay time
t
DEXT
1000 — 500 — 500 — 500 — µs Figure 22.4
Subclock stabilization
time
t
OSC3
— 4 — 2 — 2 — 2 s
Subclock oscillator
frequency
f
SUB
32.768 32.768 32.768 32.768 kHz
Subclock (φ
SUB
) cycle
time
f
SUB
30.5 30.5 30.5 30.5 µs
t
Cr
t
CL
t
Cf
t
CH
φ
t
cyc
Figure 22.3 System Clock Timing
t
OSC1
t
OSC1
EXTAL
V
CC
STBY
RES
φ
t
DEXT
t
DEXT
Figure 22.4 Oscillation Stabilization Timing