Datasheet

Section 20 Power-Down Modes
Rev.7.00 Dec. 24, 2008 Page 626 of 698
REJ09B0074-0700
20.9 Subactive Mode
20.9.1 Transition to Subactive Mode
When the SLEEP instruction is executed in high-speed mode with the SBYCR SSBY bit = 1,
LPWRCR DTON bit = 1, LSON bit = 1, and TCSR_1 PSS bit = 1, CPU operation shifts to
subactive mode. When an interrupt occurs in watch mode, and if the LSON bit of LPWRCR is 1, a
transition is made to subactive mode. And if an interrupt occurs in subsleep mode, a transition is
made to subactive mode.
In subactive mode, the CPU operates at low speed on the subclock, and the program is executed
step by step. Peripheral modules other than WDT and RTC are also stopped.
When operating the CPU in subactive mode, the SCKCR SCK2 to SCK0 bits must be set to 0.
20.9.2 Exiting Subactive Mode
Subactive mode is exited by the SLEEP instruction or the RES, MRES*, or STBY pin.
• Exiting Subactive Mode by SLEEP Instruction
When the SLEEP instruction is executed with the SBYCR SSBY bit = 1, LPWRCR DTON bit
= 0, and TCSR_1 PSS bit = 1, the CPU exits subactive mode and a transition is made to watch
mode. When the SLEEP instruction is executed with the SBYCR SSBY bit = 0, LPWRCR
LSON bit = 1, and TCSR_1 PSS bit = 1, a transition is made to subsleep mode. Finally, when
the SLEEP instruction is executed with the SBYCR SSBY bit = 1, LPWRCR DTON bit = 1,
LSON bit = 0, and TCSR_1 PSS bit = 1, a direct transition is made to high-speed mode (SCK0
to SCK2 all 0).
• Exiting Subactive Mode by RES or MRES* pin
For exiting subactive mode by the RES or MRES* pin, see section 20.4.2, Clearing Software
Standby Mode.
• Exiting Subactive Mode by STBY Pin
When the STBY pin level is driven low, a transition is made to hardware standby mode.
Note: * Supported only by the H8S/2218 Group.