Datasheet

Section 20 Power-Down Modes
Rev.7.00 Dec. 24, 2008 Page 622 of 698
REJ09B0074-0700
20.5.3 Hardware Standby Mode Timing
Figure 20.5 shows an example of hardware standby mode timing.
When the STBY pin is driven low after the RES pin has been driven low, a transition is made to
hardware standby mode. Hardware standby mode is cleared by driving the STBY pin high, waiting
for the oscillation stabilization time, then changing the RES pin from low to high.
Oscillator
RES
STBY
Oscillation
stabilization
time t
OSC1
Reset exception
handling
Figure 20.5 Hardware Standby Mode Timing (Example)
20.5.4 Hardware Standby Mode Timings
Timing of Transition to Hardware Standby Mode:
1. To retain RAM contents with the RAME bit set to 1 in SYSCR
Drive the RES signal low at least 10 states before the STBY signal goes low, as shown in
figure 20.6. After STBY has gone low, RES has to wait for at least 0 ns before becoming high.
t
2
≥ 0 ns
t
1
≥ 10 t
cyc
STBY
RES
Figure 20.6 Timing of Transition to Hardware Standby Mode
2. To retain RAM contents with the RAME bit cleared to 0 in SYSCR, or when RAM contents do
not need to be retained
RES does not have to be driven low as in the above case.