Datasheet

Section 20 Power-Down Modes
Rev.7.00 Dec. 24, 2008 Page 611 of 698
REJ09B0074-0700
20.1 Register Descriptions
The registers relating to the power down mode are shown below. For details on the low power
control register (LPWRCR), refer to section 19.1.2, Low Power Control Register (LPWRCR). For
details on the system clock control register (SCKCR), refer to section 19.1.1, System Clock
Control Register (SCKCR).
• Standby control register (SBYCR)
• System clock control register (SCKCR)
• Low power control register (LPWRCR)
• Timer control/status register (TCSR_1)
• Module stop control register A (MSTPCRA)
• Module stop control register B (MSTPCRB)
• Module stop control register C (MSTPCRC)
• Extended module stop register (EXMDLSTP)
20.1.1 Standby Control Register (SBYCR)
SBYCR performs software standby mode control.
Bit Bit Name Initial Value R/W Description
7 SSBY 0 R/W Software Standby
This bit specifies the transition mode after executing the
SLEEP instruction
0: Shifts to sleep mode when the SLEEP instruction is
executed in high-speed mode or medium-speed
mode.
Shifts to subsleep mode when the SLEEP instruction
is executed in subactive mode.
1: Shifts to software standby mode, subactive mode, or
watch mode when the SLEEP instruction is executed
in high-speed mode or medium-speed mode.
Shifts to watch mode or high-speed mode when the
SLEEP instruction is executed in subactive mode.
This bit does not change when clearing software standby
mode by using external interrupts and shifting to normal
operation. 0 should be written to this bit for clearing.